This invention relates generally to a semiconductor integrated circuit device (IC) equipped with an IIL circuit (Integrated Injection Logic), and more particularly to a technique which can be used suitably for a stacked IIL circuit.
In bipolar ICs which have a high integration (packing) density and in which analog and digital circuits are integrated on the same substrate, IIL circuits have an excellent feature in that they can be formed by the same technique as that used for analog circuits.
An IIL circuit can be operated at an operating voltage of about 0.7 V (which is approximate to the base-emitter voltage of a bipolar transistor). A conventional IC operates at 5 V, for example. For conventional IIL circuits, therefore, only about 0.7 V of the 5 V power source voltage can be utilized effectively, and the balance of 4.3 V is not used at all. In other words, the utilization rate of the power source voltage is low and the power consumption is great.
The inventors of the present invention have conducted tests to form an IIL circuit having a multi-stage structure (or a stacked structure) by connecting in series a plurality of IIL elements between the power source V.sub.cc and a ground potential (reference potential) in order to effectively utilize the power source voltage.
IIL circuits of a two-stage stacked structure have already been successfully developed by Hitachi, Ltd. However, IIL circuits with a stacked structure of three or more stages have not yet been successfully developed because a number of problems develop when additional stages are added beyond the second stage.
The present invention has been developed as a result of intensive studies on the development of IILs having a stacked structure of three or more stages.